Sunday, August 22, 2010

Integrated Circuits With Interconnects And Heat Dissipators Based On Carbon Nanostructures

Smoltek AB (Goteborg, SE) earned U.S. Patent 7,777,291 for integrated circuits having interconnects and heat dissipators based on carbon nanostructures.

According to inventor Mohammad Shafiqul Kabir, the invention generally relates to nanostructures and methods for their growth. More particularly, it relates to methods of controlling the growth of nanostructures, such as carbon nanofibers, which enables manufacture of semiconducting devices that utilize such nanostructures as interconnects and as heat dissipation media.

Relentless efforts at miniaturization are bringing traditional CMOS devices to the limit where the device characteristics are governed by quantum phenomena; in such regimes, perfect control is impossible to achieve. This has engendered a need for finding alternative new materials to fabricate devices that will possess at least the same or even better performance than existing CMOS devices but with greater control.

The miniaturization of CMOS devices has hitherto been governed by a trend--often called Moore's law--in which electronic components shrink in size by half every 30 months. The International Technology Roadmap for Semiconductors (ITRS) has established a projected growth curve according to this model. The demands for speed, high integration level, high performance and low production costs attendant on such a rate of progress are very stringent. Consequently, the problems associated with the physical and electrical characteristics of traditional materials used for making devices have escalated. Hence there is a need to search for alternative solutions to the problems that will impede the progress of silicon technology in the immediate future. This means that devising innovative materials and processes is critical to sustaining the projected rate of growth.

The ITRS emphasizes the high speed transmission needs of the chip as the driver for future interconnect development for both high performance microprocessors (MPs) and dynamic random access memory (DRAM). State of the art microprocessors are mostly made of a two dimensional layer of silicon based components, connected to one another with up to nine layers of metal interconnects. Therefore, interconnect technology plays a vital role in semiconductor technology and merits special emphasis.

The choice of new materials is however limited by factors such as compatibility with existing production methods, reproducibility of manufacture and cost. In general, the challenges of interconnect technology arise from both material requirements and difficulties in processing  Some problems that existing materials used in semiconductor technology have faced are as follows.

Currently, device performance is degraded due to high leakage current through gate oxide (which is very thin). This in turn increases the leakage current in the off state, and hence increases power consumption, which in turn can reduce the lifetime of a battery.

Cu interconnects perform poorly. Due to its low resistivity, copper is used for making interconnects that connect various components to one another, as well as to external devices and circuits. Due to the dramatic reduction in the size of the components, interconnects based on copper material are now showing poor performance in terms of current carrying capacity and lifetime of the wires, and are also becoming more difficult and costly to fabricate. In particular, a phenomenon known as electromigration threatens the reliability of nanometer-size copper interconnects at high current densities (10.sup.6 A/cm.sup.2 and above). This is a matter of concern since by the year 2013 it will be a requirement for interconnects to handle such current densities. Electromigration causes internal and external cavities that lead to wire failure.

Moreover, due to interface roughness and small grain size, the electrical resistivity of metals increases with a decrease in. Such size induced effects of metal interconnects are difficult to avoid. All of these factors in turn reduce the lifetime of a processor. No solution currently exists for interconnects that will efficiently connect the devices in a circuit with those outside of the circuit, in time to meet the projected demand for current density over the next several years.

Demand is increasing for high aspect ratio structures. Today the aspect ratio of contact holes for interconnects in DRAM stacked capacitors has reached 12:1 and is expected to increase to 23:1 by the year 2016. Creating such high aspect ratio contacts with straight walls poses substantial technological challenges, not least because void-free filling with metals (also known as vias) of such high aspect ratio features is extremely difficult.

Modern microprocessors generate inordinate amounts of heat. Heat dissipation has been increasing steadily as the transistor count and clock frequency of computer processors has increased  In particular, for example, copper interconnects of the sizes required for current and future devices generate so much heat that their electrical resistance is increased, thereby leading to a decreased capacity to carry current. Although device and system manufacturers have so far managed to channel that heat away, the task is becoming more difficult and challenging as microprocessors get faster and smaller. A practical solution for cooling of such systems that will not eventually exceed the power budget for processors has yet to be found.

In short, for all these reasons, it has become necessary to search for alternative materials and processing technology.

Carbon nanostructures, including carbon nanotubes (CNT's) and carbon nanofibers (CNF's), are considered to be some of the most promising candidates for future developments in nano-electronics, nano-electromechanical systems (NEMS), sensors, contact electrodes, nanophotonics, and nano-biotechnology. This is due principally to their one dimensional nature and their unique electrical, optical and mechanical properties. In contrast to the fullerenes, such as C60 and C70, whose principal chemistry is based on attaching specific functionalities to produce specific properties, CNTs offer almost limitless variation through design and manufacture of tubes of different diameters, pitches, and lengths. Furthermore, whereas the fullerenes offer the possibility of making a variety of discrete molecules with specific chemical properties, carbon nanotubes and carbon nanofibers provide the possibility to make molecular-scale components that have excellent electrical and thermal conductivity, and strength.  

Carbon nanotubes and carbon nanofibers have been considered for both active devices and as interconnect technology at least because of their electrical and thermal properties and their strength. For example, the high electron mobility of carbon nanotubes (79,000 cm2Ns) surpasses that of state-of-the-art MOSFET devices. Furthermore, the extremely high current carrying capacity of carbon nanotubes (1010 A/cm2)   when compared with copper interconnects (.about.10 6 A/cm2), means that carbon nanostructures potentially possess the solution to the severe problems for interconnects projected in ITRS. Additionally, copper burns out at around 10 6 A/cm2 while nanotubes and nanofibers can carry up to 109 A/ cm2. Bundles of densely packed nanostructures can also have substantially lower resistance than copper. 

FIG. 27: SEM micrographs of grown fibers on a W metal underlayer. (a) Represents the fibers grown from 100 nm dots with 500 nm pitch. All catalyst dots nucleated for growth of more than one fiber. Inset shows no break up of the catalyst after heating. (b) After growth when Ni catalyst was deposited on W directly. No growth is observed. (c) Fibers grown from prefabricated 50 nm dots with 1 .mu.m pitch. Most of the dots nucleated to grow individual fibers. (d) Individual fibers grown from 50 nm prefabricated catalyst dots with 500 nm pitch. 
FIG. 28: SEM micrograph of grown fibers on Mo metal underlayer. (a) Represents the fibers grown from a film of Ni/a-Si catalyst layer. (b) Grown fibers from a 2 .mu.m catalyst stripe. Inset picture is taken from the middle of the stripe. (c) Fibers grown from prefabricated 100 nm dots. Most of the dots nucleated to grow more than one fiber. (d) Individual fibers were grown from 50 nm prefabricated catalyst dots.

FIG. 29: shows an exemplary nano-relay device using a nanostructure. 

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