Wednesday, March 31, 2010

Micron Technology Patent Reveals Scalable High Performance Carbon Nanotube Field Effect Transistors

Micron Technology, Inc. (Boise, ID) scientist Gurtej Sandhu has developed structures and fabrication processes for producing carbon nanotube field effect transistors (FETs). The structure employs an asymmetric gate which is closer to the source and farther from the drain, which helps to minimize "off current" drain leakage when the drain is biased and the gate is otherwise off. The source and drain are preferably self-aligned to the gate, and preferably the gate is first defined as a conductive sidewall to an etched pad, according to U.S. Patent 7,687,841.

Dielectric sidewalls are then defined over the gate, which in turn defines the positioning of the source and drain in a predetermined spatial relationship to the gate. The source and drain comprise conductive sidewalls buttressing the dielectric sidewalls. The channel of the device preferably comprises randomly oriented carbon nanotubes formed on an insulative substrate and isolated from the gate by an insulative layer. The carbon nanotubes are exposed via the dielectric sidewall etch, thus ensuring the gate's self alignment with the subsequently-formed source and drain.
CNT FETs can be made with single-walled carbon nanotubes, or with multi-walled nanotubes (i.e., tubes within a tube and/or coiled sheets of carbon), and use of the disclosed techniques are likewise adaptable to the use of both types of nanotubes. Both types of tubes (single- or multi-walled) have different electrical properties, and the use of each can be benefited by the disclosed techniques by simply varying the CNT starting material (e.g., in the spin-on solvent). In fact, mixtures of single- and multi-walled carbon nanotubes could be used to fabricate a single transistor.

Moreover, the technique and transistor design disclosed are adaptable to the use of transistors which employ a single carbon nanotube as the conduction medium between the source and the drain. Should a single nanotube be used as the conduction medium, the disclosed techniques would need to be logically altered to locate such singular nanotubes at proper locations on the substrate.  

Reference to transistor terminals "source" and "drain" are synonymous in the context of an FET. Therefore, the disclosed transistor should be viewed as applicable to transistors in which the gate is also closer to the drain than to the source, as it is essentially random or a matter of preference as to what these terminals may be called in a particular transistor.

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