Carbon nanotubes are a promising material for a wide variety of applications. They are of interest due to a number of potential advantages over currently used materials, such as intrinsically small size, extremely high carrier mobility, heat conduction characteristics, mechanical strength, and others. For example, in microelectronics applications, carbon nanotubes may replace silicon in transistor applications and/or metal traces in interconnect applications, depending on the chirality and other characteristics of the carbon nanotube employed.
To utilize carbon nanotubes in some applications, it is necessary to form a single patterned carbon nanotube or patterns of well-ordered and aligned carbon nanotube arrays. However, forming patterned carbon nanotubes has many difficulties. Current techniques typically include an in situ force (e.g., electric field or flow dynamics) to direct carbon nanotube growth. Those techniques have many limitations, such as directing carbon nanotubes in only one direction (i.e., along the field lines or flow direction), which limits the arrangement and design of the carbon nanotube patterns.
Intel, in U.S. Patent Application 20090283496, reveals one of its methods to integrate patterned carbon nanotubes into semiconductor devices. Intel inventors provide structures and methods that enable the fabrication of well-ordered patterns of single carbon nanotubes and arrays of carbon nanotubes that include patterns having any chosen direction and shape through the use of growth inhibitor materials.
Intel researchers Marko Radosavljevic, Jack T. Kavalieros, Amlan Majumdar and Suman Datta have developed a method of forming a carbon nanotube pattern on a substrate surface by using an inhibitor. The carbon nanotube inhibitor directs the growth of the carbon nanotube in a well ordered fashion. The carbon nanotube inhibitor makes use of platinum.
The inhibitor pattern may be formed by well known lift-off techniques. In general, a lift-off technique includes forming a mask by lithography or other patterning technique, providing a bulk material layer over the mask, and a lift-off process to leave a pattern of the bulk material. For example, a mask that has the necessary pattern is first formed on substrate by lithography techniques. Then, a layer of material is formed over the mask, such as by a metallization step. Next, the mask is removed using a lift-off technique to leave inhibitor pattern. The lift-off technique may remove portions of the layer of material that were over the mask and leave portions of the layer of material that were over openings in the mask.
Seed pattern materials for the inhibitor include any catalyst material that provides a seed for the formation of carbon nanotubes. Intel's seed pattern includes an iron catalyst. Other seed pattern catalyst materials include suitable transition metals, such as scandium, titanium, vanadium, chromium, manganese, cobalt, nickel, copper, zinc, yttrium, zirconium, niobium, molybdenum, ruthenium, rhodium, palladium, silver, cadmium, hafnium, tantalum, tungsten, rhenium, osmium, iridium, or gold. In addition, seed pattern may include a matrix material to support the catalyst, such as aluminum oxide.