Sunday, November 29, 2009

Intel Develops Electroless Deposition Techniques for Nano and Microelectric Device Fabrication

Intel Corporation (Santa Clara, CA) scientists Shaestagir Chowdhury and Chi-Hwa Tsang developed methods of fabricating an interconnect utilizing an electroless deposition technique. Electroless deposition can be utilized in a variety of fabrication processes including the manufacturing of nano-scale devices and microelectronic machines. The technique uses a dielectric material layer with an opening extending into the dielectric material from a first surface, and electrolessly depositing a conductive material within the opening. A dual-function barrier layer is formed within the opening. The dual-function barrier layer is capable of acting as a diffusion barrier layer and a nucleation surface for a conductive material. An electrolessly deposited conductive material is formed immediately above the dual-function barrier layer. An ultra-thin seed layer may be formed immediately on top of the barrier layer prior to the electrolessly deposited conductive material being formed thereon. 

Although electroless deposition is primarily focused on forming an interconnect with metals and their alloys, the principles of the invention can be applied to any material (including plastics), any metal compounds or alloys, to any barrier materials, to nanotech devices, and the like. Electroless deposition may be used at any metallization/interconnect layer in the fabrication of a microelectronic device, according to United States Patent 7,622,382.

FIG. 9 is a cross-sectional micrograph illustrating an opening 900 having an aspect ratio of greater than about 5, filled with copper and lined with an ultra-thin seed layer 902 and a thin barrier layer 904 (not clearly visible), prior to planarization according to the present invention. As can be seen, at the entrance of the opening 900, there is no overhang and no voids are seen in the opening 900.



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