Saturday, November 21, 2009

Applied Materials Details Process for Manufacturing Low K Nano-Porous Films


Applied Materials Inc (Santa Clara, CA)  in U.S. Patent 7,611,996 details multi-stage curing of low K nano-porous films used in forming computer chips.  A combination of electron beam irradiation and thermal exposure steps may be employed to control selective outgassing of porogens incorporated into the film, resulting in the formation of nanopores, according to inventors Francimar Schmitt, Yi Zheng, Kang Sub Yim, Sang H. Ahn, Lester A. D'Cruz, Dustin W. Ho, Alexandros T Demos, Li-Qun Xia, Derek R Witty and Hichem M'Saad.   A low K layer results from  the reaction between a silicon-containing component and a non-silicon containing component featuring labile groups, and may be cured by the initial application of thermal energy, followed by the application of radiation in the form of an electron beam.


One suitable CVD plasma reactor in which a method of the present invention can be carried out is the "DLK" chamber available from Applied Materials, which is a vertical, cross-section view of a parallel plate chemical vapor deposition reactor  having a high vacuum region.  The reactor contains a gas distribution manifold  for dispersing process gases through perforated holes in the manifold to a substrate or substrate that rests on a substrate support plate or susceptor which is raised or lowered by a lift motor. A liquid injection system  such as typically used for liquid injection of tetraethyl orthosilicate (TEOS), may also be used for injecting a liquid reactant. Preferred liquid injection systems include the AMAT Gas Precision Liquid Injection System (GPLIS) and the AMAT Extended Precision Liquid Injection System (EPLIS), both available from Applied Materials, Inc.


The nano-porous silicon oxide layer can be produced by plasma enhanced (PECVD) or microwave enhanced chemical vapor deposition of a silicon/oxygen containing material that optionally contains thermally labile organic groups, and by controlled annealing of the deposited silicon/oxygen containing material to form microscopic gas pockets that are uniformly dispersed in a silicon oxide layer. The relative volume of the microscopic gas pockets to the silicon oxide layer is controlled to preferably maintain a closed cell foam structure that provides low dielectric constants after annealing. The nano-porous silicon oxide layers will have dielectric constants less than about 3.0, preferably less than about 2.5.


Applied Materials is the leading supplier of low k dielectric technology. The Applied Producer([R]) BLOk([TM]) II PECVD is a new system that delivers advanced barrier low k technology required for creating faster, more power-efficient logic chips at the 45nm node and beyond. Used in conjunction with ultralow k dielectrics, such as Applied's Black Diamond([R]) films, the BLOk II barrier film speeds signal transmission by reducing the effective k-value of the interconnect dielectric stack by up to 10%. A critical in situ pre-clean treatment, enabled by the Producer system's single wafer architecture, provides robust adhesion performance and high device reliability, with 30% higher electromigration resistance than competing barrier technologies.

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